Monolithic integrated circuits have incorporated matched devices for many years. During the evolution of the matched device technology, several design principles have become routine. For example, since semiconductor devices are temperature-sensitive, where certain components in the integrated circuit dissipate significant power desirably matched devices are located on isotherms. This is most easily effected by locating the device or devices which dissipate the most power symmetrically with respect to an axis of symmetry of the semiconductor chip containing the monolithic circuit and likewise orienting the components to be matched symmetrically about this axis. Such an approach is highly valuable in obviating another source of mismatch which arises from the stress sensitivity of semiconductor devices. The monolithic semiconductor element is generally assembled and encapsulated by the use of a material or materials which do not have exactly the same coefficient of thermal expansion as the semiconductor material itself. Thus the stress in the semiconductor die will not be equal at all points; however, when components which are desirably matched are located symmetrically with respect to a central axis of a semiconductor element with a regular shape, mismatch of electrical characteristics due to inhomogeneous stress should be minimized.
It has been traditional to mount semiconductor integrated circuits on a metallic support element by means of a hard solder eutectic bond. By choosing the metallic element to be a good match with the thermal coefficient of expansion of the silicon, the stress resulting from cool down after the attachment process is minimized. This minimizes the stress differential between components and perhaps more importantly prevents solder fatigue upon thermal cycling of the finished device. The use of plastic encapsulation may also engender inhomogeneous stress thereby causing electrical mismatch. Shifts in parameter mismatch have been found to be up to three times greater for plastic encapsulated matched devices.
Recently, the search for inexpensive encapsulation systems has led to considerations of alternatives to the thermally matched metallic mounting element and the expensive hard solders used to mount the semiconductor element thereon. In trying to achieve electrically matched devices common to a single monolithic integrated circuit encapsulated by alternative techniques, it has been found that not only is the positioning of the desirably matched elements with respect to a geometrical axis of symmetry of the semiconductor element but also the orientation of these devices with respect to the fundamental crystallographic axes of the semiconductor are important.
For silicon semiconductor elements two crystallographic orientations have been historically predominant. For devices which require epitaxial growth of a semiconductor on a single crystal semiconductor substrate, a {111} crystallographic orientation is ordinarily used, both because this orientation is favorable for epitaxial growth, the devices can be separated on natural cleavage planes, and because there are fewer problems with inhomogeneous penetration of metallic contacting means into the semiconductor element. On the other hand, a {100} orientation is most often applied in silicon MOS devices because of certain favorable device electrical characteristics which obtain by virtue of this orientation.
Regardless of the major orientation which is employed, however, generally little or no attention is given to the crystallographic orientation of the devices in the preferred plane. One exception to this general rule has been in the design of pressure transducers which often employ a bridge configuration, usually on {100} material, which exploits the difference in the piezoresistance coefficients for different directions in the plane. The published theoretical work pertaining to this problem indicates that the piezoresistance coefficient should be invariant to the position of devices made in the {111} plane. Based on these analysis one would not be led to select any particular crystallographic orientation for desirably matched devices fabricated in the {111} plane.
Two major problems are associated in the achievement of matched devices. The first of these is that the spread or standard deviation of the electrical mismatch may be so large that it is uneconomic to select only those devices having a mismatch within the desired range and discard the remainder of the devices for which there may be little or no market. Orientation of the devices along crystallographic axes which minimize their stress sensitivity could achieve reduced standard deviation and hence partially solve this yield problem. Another approach to the economic realization of matched devices is to fabricate the desirably matched component in the semiconductor wafer and then to probe the devices prior to their assembly and encapsulation in order to determine the degree of mismatch. Those devices which are unacceptable can then be marked and discarded prior to or during the assembly process. This strategy is only effective if the mismatch exhibits minimum change during the assembly and encapsulation processes.
It has been found that the first problem cited above, viz, the standard deviation of the electrical mismatch, is not substantially effected by device orientation in a {111} plane. That is, the spread is essentially independent of orientation so that there is no particular advantage to any given crystallographic orientation in terms of the potentially achievable number of devices which match within the desired tolerances. However, it has been discovered that desirably matched devices oriented with mirror symmetry about a &lt;211&gt; direction in a {111} plane exhibit vastly reduced changes in the mean value of the distribution when the values in wafer form are compared to those obtaining after assembly and encapsulation. The temperature coefficient of the mismatch is also greatly reduced. The shift in the mean value of the distribution is vastly enhanced for devices with non-optimal orientation for the case where the devices are mounted on a thermally mismatched supporting element. It has been traditional in the semiconductor industry to lay out individual rectilinear circuit elements parallel to one of the separation lines of the resulting die; these lines are often parallel or perpendicular to a (110) "flat" formed on the silicon crystal from which the substrate is cut. That a statistically insignificant number of samples of the optimum orientation has been observed on silicon integrated circuit dice is imputed to accident in view of the observation of many other integrated circuit dice with disadvantageous orientations according to the present invention.